I. Field of the Disclosure
The technology of the disclosure relates generally to complementary metal oxide semiconductor (CMOS) standard library cell circuits, and specifically to adjusting threshold voltages of transistors within such circuits.
II. Background
Processor-based computer systems can include a vast array of integrated circuits (ICs). Each IC has a complex layout design comprised of multiple IC devices. Standard library cell circuits are often employed to assist in making the design of such ICs less complex and more manageable. In particular, standard library cell circuits provide a designer with pre-designed cells corresponding to commonly used IC devices that conform to specific design rules of a chosen technology. As non-limiting examples, standard library cell circuits may include gates, inverters, multiplexers, and adders. Using standard library cell circuits enables a designer to create ICs having consistent layout designs, thereby creating a more uniform and less complex layout design across multiple ICs, as compared to custom designing each circuit.
However, multiple instances of an IC designed with standard library cell circuits can have different timing properties based on how manufacturing process variations affect the speed of the silicon die on which each instance of the IC is fabricated. For example, an IC fabricated on a first silicon die can have timing properties that vary from an identical IC fabricated on a second silicon die if the two silicon die have different speeds as a result of manufacturing process variations. In this manner, a silicon die can have a corresponding speed that is considered slow, typical, or fast as compared to the expected speed of silicon. Thus, an IC can be designed using standard library cell circuits to meet a specific design timing target, but variations in the speed of silicon as a result of manufacturing process variations can require additional steps to remedy the timing differences existing between separate instances of the IC.
One solution to overcome timing differences caused by varying silicon die speeds involves adding timing closure elements to an IC. For example, clock buffers may be added at various locations within the layout of an IC to adjust the timing of the IC to reach the design timing target. The timing closure elements can alter the timing of an IC so as to overcome a discrepancy in timing between the design timing target and the actual timing caused by the speed of the silicon. However, adding such timing closure elements to the IC layout design increases the area and power consumption of the IC. Thus, it would be advantageous if an IC designed with standard library cell circuits could achieve design timing targets without requiring timing closure elements to overcome timing discrepancies caused by silicon speeds.